西安电子科技大学学报（自然科学版）Issue(1)：10-15,6.DOI:10.3969/j.issn.1001-2400.2015.01.002
256 MHz采样71 dB动态范围连续时间ΣΔAD C设计
Continuous timeΣΔADC design with 256 MHz sampling and 7 1 dB DR
摘要
Abstract
A wide bandwidth continuous timeΣΔADC is widely used in the wireless communication field. AΣΔADC with the 3 order 4 bit modulator is designed with the 256 MHz sampling frequency.In order to reduce the clock jitter, the nonreturn-to-zero (NRZ) DAC feedback pulse is used. And the loop asynchronous problem is improved by introducing a half of clock cycle delay.Also how to reduce the effect of the DAC mismatch is discussed.A low voltage,low power,and high speed operational amplifier is designed with feedforward compensation technology.Finally,based on the 0.1 3μm technology,the SNDR is 62.5 dB and DR is 71 dB with a 1.2V supply.关键词
模数转换器/连续时间/ΣΔ型数模转换器Key words
analog to digital converter/continuous time/sigma delta analog to digital converter分类
信息技术与安全科学引用本文复制引用
杨银堂,袁俊,张钊锋..256 MHz采样71 dB动态范围连续时间ΣΔAD C设计[J].西安电子科技大学学报（自然科学版）,2015,(1):10-15,6.基金项目
国家重大专项资助项目(2010ZX03006-003-02) （2010ZX03006-003-02）
