陕西科技大学学报（自然科学版）Issue(1)：155-159,5.
基于 Vivado HLS 的 FPGA 开发与应用研究
Development and application of FPGA based on Vivado HLS
摘要
Abstract
In order to more rapid implementation of digital signal processing and image pro‐cessing algorithm in hardware design. Vivado High‐Level Synthesis (HLS) design tools can be used in the design and development of Zynq All programmable with FPGA. HLS can transform a C or C++ design specification into a Register Transfer Level implementation which can be synthesized into a Xilinx FPGA. Compared with Veirlog or VHDL design, this tool will reduce development cycles and costs of FPGA. This paper describes the characteris‐tics and applications of HLS in detail. With the examples of image posterization and loop en‐coder, we can learn the design method and skills.关键词
高层次综合/Vivado/FPGAKey words
high level synthesis/Vivado/FPGA分类
信息技术与安全科学引用本文复制引用
党宏社,王黎,王晓倩..基于 Vivado HLS 的 FPGA 开发与应用研究[J].陕西科技大学学报（自然科学版）,2015,(1):155-159,5.基金项目
西安市科技计划项目 （）
