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An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs

Yao Qiang Ye Zuochang Yu Wenjian

半导体学报（英文版）2015，Vol.36Issue(8)：150-156,7.

半导体学报（英文版）2015，Vol.36Issue(8)：150-156,7.DOI:10.1088/1674-4926/36/8/085006

An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs

Yao Qiang ¹Ye Zuochang ¹Yu Wenjian²

作者信息

1. Institute of Microelectronics, Tsinghua University, Beijing 100084, China
2. Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
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摘要

关键词

3D IC/through silicon via (TSV)/parasitic extraction/floating random walk algorithm/metal-oxide-semiconductor (MOS) capacitance

Key words

3D IC/through silicon via (TSV)/parasitic extraction/floating random walk algorithm/metal-oxide-semiconductor (MOS) capacitance

引用本文复制引用

Yao Qiang,Ye Zuochang,Yu Wenjian..An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs[J].半导体学报（英文版）,2015,36(8):150-156,7.

基金项目

Project supported by the National Natural Science Foundation of China (No.61422402),and the Tsinghua University Initiative Scientific Research Program. （No.61422402）

半导体学报（英文版）

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ISSN：1674-4926

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