现代电子技术2015，Vol.38Issue(17)：61-64,4.
FPGA/CPLD的管脚设置对信号完整性的影响分析研究
Analysis and research on influence of FPGA/CPLD pins setting on signal integrity
摘要
Abstract
With the appearance and usage of FPGA and CPLD in modern electronic circuits,as well as the higher integrity and the faster speed of electronic devices,more rigorous requirements for the stability of electronic circuits are presented,which manifest as,the rigorous requirements of system′s power supply integrity and signal integrity on hardware. In the view of signal integrity,the Altera Cyclone IV FPGA is studied emphatically by analyzing the problems which are easy to ignore by hardware and software engineers. The stability and robustness of FPGA/CPLD system are guaranteed by hardware.关键词
FPGA/CPLD/时序/信号完整性Key words
FPGA/CPLD/timing sequence/signal integrity分类
信息技术与安全科学引用本文复制引用
郭利文,邓月明,莫晓山..FPGA/CPLD的管脚设置对信号完整性的影响分析研究[J].现代电子技术,2015,38(17):61-64,4.基金项目
全国工程专业学位研究生教育自选课题(2014-JY-074) （2014-JY-074）
湖南省普通高校教学改革研究项目(湘通教[2012]401号) （湘通教[2012]401号）
湖南省普通高校实践教学建设项目(湘教通(2013)295号) （湘教通(2013）
湖南省自然科学基金资助项目(13JJ6031)的资助 （13JJ6031）
湖南师范大学第三批产学研合作示范基地项目(20140616-01) （20140616-01）
