物理学报Issue(2)：1-7,7.DOI:10.7498/aps.64.026601
三维集成电路堆叠硅通孔动态功耗优化∗
Stack-through silicon via dynamic p ower consumption optimization in three-dimensional integrated circuit
摘要
Abstract
Stack-through silicon via (TSV) used in three-dimensional integrated circuit has good temperature and heat transfer characteristics. A novel model for optimizing the dynamic power consumption based on stacked-TSV is proposed in this paper, in which delay, area and minimum aperture are comprehensively considered. After extracting single TSV parasitic electrical parameters, we analyze the influences of TSV size on multilayer TSV power consumption and delay performance, thereby building the hierarchical reduction TSV structure step by step. Moreover, the influences of TSV height and thickness of oxide layer are discussed. Results show that the model can significantly improve the dynamic power consumption at the expense of little delay. The power consumption optimization reduction is up to 19.52% with 5%delay penalty.关键词
三维集成电路/堆叠硅通孔/动态功耗/延时Key words
3D integrated circuit/stack-through silicon via/dynamic power consumption/delay引用本文复制引用
董刚,武文珊,杨银堂..三维集成电路堆叠硅通孔动态功耗优化∗[J].物理学报,2015,(2):1-7,7.基金项目
国家自然科学基金(批准号:61334003)资助的课题.@@@@* Project supported by the National Natural Science Foundation of China (Grant No.61334003) （批准号:61334003）
