兵工自动化Issue(7)：86-88,3.DOI:10.7690/bgzdh.2013.07.025
基于VerilogHDL的异步串行通信IP核设计
IP Core Design of Asynchronous Serial Communication Based on VerilogHDL
李健 1吕胜涛2
作者信息
- 1. 中国兵器工业第五八研究所军品部，四川 绵阳 621000
- 2. 中国人民武装警察部队装备研究所，北京 100012
- 折叠
摘要
Abstract
For improving CPU work efficiency, asynchronous serial communication IP core based on VerilogHDL is designed. Introduce asynchronous serial communication principle, Nios II embedded processor system structure and Avalon bus feature, analyze realization method of asynchronous serial communication, put forwards interface relation of each function module. Designed and achieved the IP core of serial communication, it can be used easily by Sopc Builder and can correctly execute the function of receive and transmit of asynchronous serial data. The example proved that the design not only realize the correct communication of serial port, but also can be used convenient and get a better communication.关键词
串行通信/VerilogHDL/IP核Key words
serial communication/verilogHDL/IP core分类
军事科技引用本文复制引用
李健,吕胜涛..基于VerilogHDL的异步串行通信IP核设计[J].兵工自动化,2013,(7):86-88,3.
