湖南大学学报（自然科学版）Issue(10)：78-82,5.
一种高性能数字输出端口电路设计∗
A Design for High-performance Digital Output I/O Circuit
摘要
Abstract
In the digital output port of the traditional multi-power system,there are pull-up-drop-down competition and serious asymmetry between positive edge and negative edge,which results in a large delay-power product,while the large voltage fluctuation and spurious triggering result in a high SSN noise.To deal with these problems,this paper proposed a novel output circuit architecture,which employs a quick voltage level transform circuit to reduce the delay-power product and a resistance of ground bounce output structure to reduce the SSN noise.The output circuit was fabricated by SMIC18mmrf process,and the test shows that the delay-power consumption product is reduced by 5%~1 5% and SNN noise amplitude is low-ered by 30%,compared with the traditional circuit,which indicates the high performance of the novel out-put circuit.关键词
噪声减少/转换电路/电平转换/同步开关噪声(SSN)/延时功耗积/地弹效应/功耗/阈值电压Key words
noise abatement/switching circuits/level transform/Simultaneous Switch Noise(SSN)/delay-power product/ground bounce/power consumption/threshold voltage分类
信息技术与安全科学引用本文复制引用
陈迪平,陈思园,曾健平..一种高性能数字输出端口电路设计∗[J].湖南大学学报（自然科学版）,2015,(10):78-82,5.基金项目
湖南省工业支撑计划项目(2013GK3019) （2013GK3019）
湖南省科技计划资助项目(2014GK3148) （2014GK3148）
