摘要
Abstract
The paper describes a high-speed floating point adder design, which achieves compliance with IEEE-754 standard single-precision, double-precision, extended-double-precision and integer data with rounding mode controlled, working under X87 execution environment. The design is based on Two-Path algorithm with parallel pipeline depth optimization algorithm. The paper puts forward a deep parallel pipeline design. After verification the function meets the design requirements, using TSMC 65 nm technology library, whose operating frequency is up to 900 MHz.关键词
浮点加法器/IEEE-754/Two-Path 算法/并行流水线Key words
floating point adder/IEEE-754/Two-Path algorithm/parallel pipeline分类
计算机与自动化
