现代电子技术Issue(16)：133-136,4.
基于改进型选择进位加法器的32位浮点乘法器设计
Design of 32-bit floating-point multiplier based on improved carry-select adder
刘容 1赵洪深 2李晓今1
作者信息
- 1. 中国科学院 光电技术研究所，四川 成都 610209
- 2. 中国科学院，北京 100049
- 折叠
摘要
Abstract
On the basis of the modified Booth encoding,Wallace tree structure and carry-select adder,a new structure of 32-bit float point multiplier is proposed,which can shorten its critical path delay by cutting the carry chain. The carry selection of each level of the carry-select adder comes from the upper carry output. The new structure can produce the 16th bit of the man-tissa. By comparing it with the relative output bit of the Wallace tree,the carry which comes from the former bit can be got to achieve the carry selection. By using the new structure,a 4-stage pipeline float point multiplier supporting IEEE754 standard is implemented on Altera’s FPGA device EP2C70F896C6. The time-sequence simulation shows that the critical path delay of the multiplier is 5.9 ns,less than that of the traditional multiplier,which is 6.4 ns.关键词
修正Booth算法/Wallace树结构/选择进位加法器/浮点乘法器Key words
modified Booth encoding/Wallace tree structure/carry-select adder/float-point multiplier分类
信息技术与安全科学引用本文复制引用
刘容,赵洪深,李晓今..基于改进型选择进位加法器的32位浮点乘法器设计[J].现代电子技术,2013,(16):133-136,4.
