现代电子技术Issue(19)：94-97,101,5.
频率计权网络的数字电路实现
Implementation of digital circuit for frequency weighting network
赵丹 1李丽 2贺慧勇 1刘嘉文 2廖文平 1王燕 1商梅雪 1魏明生1
作者信息
- 1. 长沙理工大学 物理与电子科学学院，湖南 长沙 410114
- 2. 广东电网公司 电力科学研究院，广东 广州 510080
- 折叠
摘要
Abstract
An implementation scheme of digital circuit for frequency weighting network is presented. The frequency weighting filter generated by the filter design tool is described in detail,which is converted into transplantable and synthesizable HDL code by using HDL code generation tool,and can be implemented on FPGA. The test process of the filter model was simulated and verified respectively by software and hardware. The test results show that the designed frequency weighting network conforms to weighting characteristic and tolerance standard,and can simplify circuit structure and operation,reduce power consumption and the cost,save resources and improve efficiency. The frequency weighting value of the signal can be obtained quickly.关键词
频率计权/HDL代码/数字电路/FPGA仿真Key words
frequency weighting/HDL code/digital circuit/FPGA simulation分类
信息技术与安全科学引用本文复制引用
赵丹,李丽,贺慧勇,刘嘉文,廖文平,王燕,商梅雪,魏明生..频率计权网络的数字电路实现[J].现代电子技术,2015,(19):94-97,101,5.
