现代电子技术2015，Vol.38Issue(21)：145-148,4.DOI:10.16652/j.issn.1004-373x.2015.21.039
基于Sklansky结构的24位并行前缀加法器的设计与实现
Design and implementation of 24-bit parallel prefix adder based on Sklansky structure
摘要
Abstract
Aiming at the delay problem of serial carry adder(SCA),a parallel prefix adder(PPA)based on Sklansky was adopted. A 24-bit PPA was designed and realized on the basis of optimizing the various modules of PPA. By comparing the delay of 24-bit PPA with that of 24-bit SCA,the results show that the parallel prefix adder based on Sklansky can increase the com-puting speed effectively.关键词
并行前缀加法器/Sklansky结构/优化延时/并行思想Key words
parallel prefix adder/Sklansky structure/optimization delay/parallel thinking分类
信息技术与安全科学引用本文复制引用
姚若河,马廷俊,苏少妍..基于Sklansky结构的24位并行前缀加法器的设计与实现[J].现代电子技术,2015,38(21):145-148,4.基金项目
国家自然科学基金项目(61274085) （61274085）
华南理工大学中央高校基本科研学生项目(10561201435) （10561201435）
