现代电子技术2016，Vol.39Issue(1)：62-64,3.DOI:10.16652/j.issn.1004-373x.2016.01.017
分数倍内插成形滤波器设计及实现
Design and implementation of fractional interpolation shaping filter
彭卫 1吴兵 1李武建1
作者信息
- 1. 中国电子科技集团公司 第三十八研究所,安徽 合肥 230031
- 折叠
摘要
Abstract
An implementation method of fractional interpolation shaping filter is proposed and realized on FPGA. The filter can realize the fractional conversion between the input rate and the rate after interpolation shaping filtering,adjust itself with the changes of input rate in real-time,and break through the limitation on the input rate of the traditional integer interpolation shaping filter. The filter were realized,in which the input rate is 1 KS/s~50 MS/s,stepping is 1 S/s,output rate is 100~2 000 MS/s, interpolation multiple is larger than 4,and fractional delay precision is Tclk 65 536 . The filter has the advantages of few FPGA resource occupation,simple interface,high flexibility and applicability,and can extend its variable rate range as necessary.关键词
分数倍内插/成形滤波器/内插滤波器/FPGA/无线通信Key words
fractional interpolation/shaping filter/interpolation filter/FPGA/wireless communication分类
信息技术与安全科学引用本文复制引用
彭卫,吴兵,李武建..分数倍内插成形滤波器设计及实现[J].现代电子技术,2016,39(1):62-64,3.
