重庆邮电大学学报（自然科学版）Issue(1)：60-65,6.DOI:10.3979/j.issn.1673-825X.2016.01.009
一种改进的 QC-LDPC 码及其编码器 FPGA 实现
An improved structure of QC-LDPC codes and its FPGA encoder implementation
卫霞 1张文俊2
作者信息
- 1. 西北工业大学 明德学院 电子信息工程系，西安 710124
- 2. 陕西省通信管理局，西安 710075
- 折叠
摘要
Abstract
In order to increase encoding rate flexibility and reduce its operation complexity,an improved structure of QC-LDPC codes is proposed,and several high rate codes were designed.Simulation result shows that the performance of the improved LDPC codes is better than that of conventional QC-LDPC codes in moderate and long frame length.An encoding architecture based on RAMis designed.The encoder stores the check matrix by storing address-pointers,thus multi-rate encoding is flexible.The encoder is implemented with Verilog HDL language on the chip of Spartan 3 XC3S1 500.Synthesis reports show that the systems maximum frequency is 225.1 74 MHz with less resource and the same encoding time-delay of normal QC-LDPC encoder based on shift-register.关键词
低密度准循环奇偶校验码/基于 RAM的编码器/变码率编码Key words
quasi-cyclic low density parity check codes/encoder based on RAM/multi-rate encoding分类
信息技术与安全科学引用本文复制引用
卫霞,张文俊..一种改进的 QC-LDPC 码及其编码器 FPGA 实现[J].重庆邮电大学学报（自然科学版）,2016,(1):60-65,6.
