电子器件Issue(1)：62-66,5.DOI:10.3969/j.issn.1005-9490.2016.01.013
DDS激励PLL高性能频率合成器设计
A High Performance Synthesizer Design Based on DDS Driving PLL
付钱华 1易淼2
作者信息
- 1. 西华大学电气与电子信息学院，成都610039
- 2. 电子科技大学信息与软件工程学院，成都610054
- 折叠
摘要
Abstract
A high resolution P-band synthesizer with low spurious and low phase noise was developed for fitting to all types of CDMA RF transceiver LO application requirements. The characteristic that DDS output signal has high resolution and PLL has narrowband tracking filter was full used,the defect of DDS was avoided,which narrow band spurious are hardly eliminated,the wideband spurious of DDS that caused by DAC nonlinearity and amplitude quan⁃tization error are restrained effective,through frequency planning and parameters configuration. The feasibility of scheme is analyzed by simulation,a synthesizer sample is developed and tested. The result shows its output frequen⁃cy range is 755 MHz~765 MHz,frequency resolution is 100.5 kHz,spurious is better than-71 dBc,phase noise is better than-105 dBc/Hz@1 kHz.关键词
通信技术/杂散抑制/频率合成/相位噪声/锁相环(PLL)Key words
communication technology/spurious suppression/frequency synthesis/phase noise/phase locked loop分类
信息技术与安全科学引用本文复制引用
付钱华,易淼..DDS激励PLL高性能频率合成器设计[J].电子器件,2016,(1):62-66,5.
