电子器件Issue(1)：94-97,4.DOI:10.3969/j.issn.1005-9490.2016.01.020
基于CML的高速数据传输电路设计
Design of High-Speed Data Transmission Circuit Based on the CML
马放 1任勇峰 1单彦虎 1彭巧君1
作者信息
- 1. 中北大学电子测试技术国家重点实验室，太原030051
- 折叠
摘要
Abstract
A design of high-speed data transmission circuit based on the CML data transfer standard was proposed, which is an important developing for the present situation of the increasingly larger amount of data and faster data transmission speed. The circuit combines FPGA controller and TLK1501 as protocol chip whose internal encoding method is 8 bit/10 bit and interface standards is CML to realize high speed data transmission. It amended the logic control due to the timing constraints of the clock signal and solved the problem of bit errors due to the distortion of the internal clock. The experimental results show that the circuit has a high stability and reliability.关键词
CML/时序约束/8 b/10 b编码/TLK1501Key words
CML/Timing constraints/8 b/10 b encoding/TLK1501分类
信息技术与安全科学引用本文复制引用
马放,任勇峰,单彦虎,彭巧君..基于CML的高速数据传输电路设计[J].电子器件,2016,(1):94-97,4.
