西安电子科技大学学报（自然科学版）Issue(1)：162-166,172,6.DOI:10.3969/j.issn.1001-2400.2016.01.029
用于8位80 MS/s 模数转换器的增益数模单元电路
Optimum design of the MDAC circuit for the 8 bit 80 MS/s pipelined A/D converter
摘要
Abstract
A high speed and medium accuracy multiplying digital-to-analog converter ( MDAC ) circuit optimization design is presented for meeting the requirements of the 8 bit , 80 MS/s pipelined analog-to-digital ( A/D) converter . An optimized transmission gate is adopted to improve the linearity of the MDAC circuit . In view of the high gain two-stage operational amplifier , design method in wideband operational amplifier design optimization is proposed and the settling time and power consumption of operational amplifier can be effectively decreased In addition , an improved high speed dynamic comparator is used in this design Fabricated in a 1.8 V 0.18 μm CMOS process , this A /D converter with the proposed MDAC circuit achieves a signal to noise and distortion ratio ( SNDR) of 54.6 dB and an effective number of bits ( ENOB) of 7.83 bit with a 35 M Hz input signal at the 80 M Hz sample rate .关键词
增益数模单元/运放优化/传输门/动态比较器/流水线模数转换器Key words
multiplying digital-to-analog converter/amplifier optimization/transmission gate/dynamic comparator/pipelined analog-to-digital converter分类
信息技术与安全科学引用本文复制引用
董嗣万,朱樟明,刘敏杰,杨银堂..用于8位80 MS/s 模数转换器的增益数模单元电路[J].西安电子科技大学学报（自然科学版）,2016,(1):162-166,172,6.基金项目
国家自然科学基金资助项目 （）
