西安电子科技大学学报（自然科学版）2016，Vol.43Issue(2)：35-40,6.DOI:10.3969/j.issn.1001-2400.2016.02.007
高效低存储DWT的VLSI结构设计
Highly efficient VLSI architecture for DWT with low-storage implementation
摘要
Abstract
With the gradual increase in image resolution of the spacecraft camera, it is highly required to figure out the problem how to process a huge amount of image data on board at a high speed. As a solution, the CCSDS proposes a space-oriented image-coding standard. For the sake of high image-coding performance, it adopts wavelet transformation as a method of image data transformation. However, wavelet transformation contains multi-level data processing, which causes more computational time consumption and more memory utilization. In order to solve this problem, we propose a highly efficient VLSI architecture for DWT with low-storage. By revising the traditional lifting structure and employing time-multiplex data processing strategy to perform the second and third level of wavelet transformation by the same logic module, the usage of logic resource is reduced with no sacrifice on speed.Using a small amount of on-chip memory instead of off-chip memory to save certain parts of DWT coefficients and sending the coefficients in a specific sequence to entropy coder timely, the off-chip memory for storage of DWT coefficients is no longer required. The proposed VLSI architecture of DWT is already implemented on the Xilinx FPGA XC4VSX55, which can achieve a high performance, in terms of data throughput, reaching 95.91MPixels/s.关键词
图像处理/离散小波变换/现场可编程门阵列/超大规模集成电路Key words
image processing/discrete wavelet transform ( DWT )/field programmable gate array ( FPGA)/very large scale integration( VLSI)分类
信息技术与安全科学引用本文复制引用
董明岩,雷杰,王柯俨,李云松..高效低存储DWT的VLSI结构设计[J].西安电子科技大学学报（自然科学版）,2016,43(2):35-40,6.基金项目
国家优秀青年基金资助项目(61222101) （61222101）
国家自然科学基金资助项目(61301287 ,61301291) （61301287 ,61301291）
高等学校学科创新引智计划资助项目(B08038) （B08038）
中央高校基本科研业务费专项资金资助项目(K5051301043) （K5051301043）
