计算机应用与软件2016，Vol.33Issue(5)：13-16,4.DOI:10.3969/j.issn.1000-386x.2016.05.004
基于改进的 Booth 编码和 Wallace 树的乘法器优化设计
AN OPTIMISED DESIGN OF MULTIPLIER BASED ON IMPROVED BOOTH ENCODING AND WALLACE TREE
摘要
Abstract
According to the problem that multiplier can’t take into account both the path delay and layout area,we proposed a novel structure of 32 bit signed multiplier.Its characteristics are:the multiplier uses the improved Booth encoding to generate a partial product array ranging regularly,and the circuit it brought forth reduces the delay and area compared with traditional method;it employs the improved novel Wallace tree compressing structure which is the combination of 4 -2 compressor and 3 -2 compressor,and to compress 17 partial products into 2 ones only needs 10 XOR-delays,thus speeds up multiplication computation considerably.The whole design was verified on FPGA,and synthesised with SMIC 0.18 μm-based standard unit process.Synthesis results showed that the chip area was 0.1127 mm2 ,and the key path delay was 3.4 ns.Experimental results also showed that the improved multiplier reduced both the key path delay and the layout area.关键词
乘法器/Booth 编码/部分积阵列/Wallace 树Key words
Multiplier/Booth encoding/Partial product array/Wallace tree分类
信息技术与安全科学引用本文复制引用
石敏,王耿,易清明..基于改进的 Booth 编码和 Wallace 树的乘法器优化设计[J].计算机应用与软件,2016,33(5):13-16,4.基金项目
广东省工程技术研究中心项目（2012gczx A003）。 （）
