无线电工程2016，Vol.46Issue(7)：71-75,5.DOI:10.3969/j.issn.1003-3106.2016.07.19
基于FPGA的冗余CAN总线通信节点设计
Design of Redundancy CAN Bus Communication Node Based on FPGA
摘要
Abstract
In view of the requirements for high reliability of the communication system in aerospace field,a design of redundancy CAN bus node is proposed based on FPGA,SJA1000 and PCA82C250.The selection principle of CAN bus redundancy mode is intro-duced,the hardware design of CAN bus node with controller redundancy and the design of the FPGA control program are described in detail.Then,the paper focuses on explaining the initialization flow of SJA1000,message sending/receiving process,error handling of SJA1000 and data selection strategy under hot backup condition of the link.The control timing of SJA1000 is verified by the simulation result of the FPGA program,and finally the transmission performance test under high and low temperature and the function test of redun-dancy data processing are made.The test results prove that the CAN bus node has high real-time performance and high stability,and the design is suitable for many fields which require high reliability such as space field and aviation field.关键词
CAN总线/FPGA/冗余/CAN控制器/SJA1000Key words
CAN bus/FPGA/redundancy/CAN controller/SJA1000分类
信息技术与安全科学引用本文复制引用
孙大元,闫冬..基于FPGA的冗余CAN总线通信节点设计[J].无线电工程,2016,46(7):71-75,5.基金项目
国家高技术研究发展计划（“863”计划）基金资助（ SS2015AA011303）。 （）
