高技术通讯2016，Vol.26Issue(3)：226-234,9.DOI:10.3772/j.issn.1002-0470.2016.03.002
基于软硬件协同设计的解释器指令分派方法
An instruction dispatch approach using hardware-software co-design for interpreters
摘要
Abstract
To reduce the overhead caused by instruction dispatch to improve the performance of interpreters , an instruc-tion dispatch approach based on hardware and software co-design is proposed .Its main idea is to eliminate the ex-pensive operation of constant address loading by optimizing the instruction dispatch table in the aspect of sofware , and to acceleratethe speed of memory access under the support of hardware by enhancing the processor ’ s instruction set in the aspect of hardware .The hardware-software co-design can minimize the runtime overhead of instruction dispatch , thus improving the performance of interpreters .The experimental results showed that the proposed ap-proach significantly improved the performance of interpreters .For benchmarks of SPECjvm 98 and DaCapo , the overall performance of interpreters was improved by 11.5%, and the highest performance boost was up to 15.4%. The approach is highly versatile , easy to implement and can be applied to the design and implementation of high performance interpreters on mainstream processors .关键词
解释器/指令分派/软硬件协同设计/虚拟机/优化Key words
interpreter/instruction dispatch/hardware and software co-design/virtual machine/optimization引用本文复制引用
傅杰,靳国杰,章隆兵,王剑..基于软硬件协同设计的解释器指令分派方法[J].高技术通讯,2016,26(3):226-234,9.基金项目
国家“核高基”科技重大专项课题（2009ZX01028－002－003，2009ZX01029－001－003，2010ZX01036－001－002，2012ZX01029－001－002－002，2014ZX01020201，2014ZX01030101），国家自然科学基金（61221062，61133004，61173001，6123009，61222204，61432016）和863计划（2012AA010901，2013AA014301）资助项目。 （）
