西安电子科技大学学报（自然科学版）2016，Vol.43Issue(4)：23-28,6.DOI:10.3969/j.issn.1001-2400.2016.04.005
一种双采样1.2V 7位125 MS/s流水线 ADC的设计
Design of double sample 1. 2 V 7 bit 125 MS/s pipelined ADC
摘要
Abstract
A 7 bit 125 MS/s double sample pipelined ADC which can achieve a low power and a high performance for the SoC system is presented . The presented ADC with op‐amp sharing between two channels and a new timing scheme can not only eliminate sampling timing skew , but also has a low power and a small area . Test results show that the ADC designed in a 0.13μm CMOS process achieves a maximum SNDR of 43.38 dB , and that ENOB is 6.8 bits . The ADC consumes 10.8 mW at 125 MS/s under a 1.2 V supply voltage .关键词
双采样/运放共享/时间交织/流水线型模数转换器Key words
double sample/op-amp sharing/time-interleaved/pipelined analog to digital converter分类
信息技术与安全科学引用本文复制引用
王晓飞,郝跃..一种双采样1.2V 7位125 MS/s流水线 ADC的设计[J].西安电子科技大学学报（自然科学版）,2016,43(4):23-28,6.基金项目
国家自然科学基金资助项目 （）
