计算机工程与应用2016，Vol.52Issue(17)：247-252,6.DOI:10.3778/j.issn.1002-8331.1410-0225
0.0013mm2自动频率校正算法电路的设计及应用
Design and application of 0.0013 mm2 automatic frequency calibration algorithm circuit
摘要
Abstract
In high-speed serial interface design of PCIE2.0, in order to make data transmission more accurately, the work-ing clock which serial transferred data needs should be locked in a very short time. In order to reduce PLL lock time and improve clock stability, a new binary searching algorithm automatic frequency calibration circuit is proposed based on tra-ditional sequential searching algorithm circuit and applied in the 5 GHz frequency synthesizer. The maximum correction time is 22.5μs. Frequency synthesizer is taped out in SMIC 55 nm CMOS process, under SS corner, the area of automatic frequency calibration circuit is only 0.0013 mm2. After testing, PLL can lock in a short time and has a perfect performance.关键词
锁相环(PLL)/自动频率校正(AFC)/顺序搜索/二进制搜索/锁定时间Key words
Phase Locked Loop(PLL)/Automatic Frequency Calibration(AFC)/sequential search/binary search/lock time分类
信息技术与安全科学引用本文复制引用
汪波,胡锦,张锋,赵建中..0.0013mm2自动频率校正算法电路的设计及应用[J].计算机工程与应用,2016,52(17):247-252,6.基金项目
国家高技术研究发展计划（863）（No.2011AA010403）；湖南省科技计划项目（No.2014GK3002）。 （）
