太赫兹科学与电子信息学报2016，Vol.14Issue(4)：606-609,4.DOI:10.11805/TKYDA201604.0606
基于晶振倍频鉴相的C波段低相噪频率源设计
Design of a C-band low phase noise frequency synthesizer based on phase detecting with crystal oscillator multiplication
董洪新 1邰战雄 1李强 1杨洋 1朱中浩 1宋烨曦1
作者信息
- 1. 四川九洲电器集团有限责任公司，四川绵阳 621000
- 折叠
摘要
Abstract
The phase noise composition and characteristics of a digital Phase Locked Loop(PLL) are investigated. A phase locked frequency synthesizer based on crystal oscillator multiplication is presented. Compared with the traditional frequency synthesizer based on single PLL,the proposed design achieves lower phase noise. According to the test results,the phase noise of -109.1 dB/Hz@10 kHz is achieved by the traditional approach when the output is 6 480 MHz; while a better phase noise performance of -117 dB/Hz@ 10 kHz is reached by the proposed design at the same frequency,using the same crystal oscillator PLL chip and Voltage Controlled Oscillato(VCO), which is improved by 8 dB compared to the traditional design.关键词
低相位噪声/倍频/锁相环Key words
low phase noise/frequency multiplication/Phase Locked Loop分类
信息技术与安全科学引用本文复制引用
董洪新,邰战雄,李强,杨洋,朱中浩,宋烨曦..基于晶振倍频鉴相的C波段低相噪频率源设计[J].太赫兹科学与电子信息学报,2016,14(4):606-609,4.
