高技术通讯2016，Vol.26Issue(6)：542-549,8.DOI:10.3772/j.issn.1002-0470.2016.06.004
低功耗高速时钟数据恢复电路
A low power architecture of high-speed clock and data recovery circuit
摘要
Abstract
To reduce the power consumption of the clock and data recovery ( CDR) circuit of a high speed serial inter-face, a novel phase detecting CDR was presented and it was implemented based on the study of existing CDR algo-rithms.The new design only used one sampling clock under high speed, so the sample rate can be reduced to half of the traditional phase detecting architecture and the power consumption of the front sampler can be reduced.The proposed phase detecting algorithm employed a statistic method to diminish the clock jitter during phase detecting period to reach lower bit error rate ( BER) .The phase detecting algorithm can be implemented using digital synthe-sis method and it works at lower frequency so it can be easily port to other technologies.The whole circuits was manufactured using 40nm CMOS technology, and the chip test results demonstrated that the designed architecture worked at 13Gb/s with the BER less than 10E-12 and the power efficiency was 0.83pJ/bit.关键词
低功耗接收端,高速串行接口,时钟数据恢复(/CDR)Key words
low power receiver/high-speed serial interface/clock and data recovery ( CDR)引用本文复制引用
孟时光,杨宗仁..低功耗高速时钟数据恢复电路[J].高技术通讯,2016,26(6):542-549,8.基金项目
国家"核高基"科技重大专项课题(2009ZX01028-002-003, 2009ZX01029-001-003, 2010ZX01036-001-002, 2012ZX01029-001-002-002, 2014ZX01020201, 2014ZX01030101),国家自然科学基金(61521092, 61133004, 61173001, 61232009, 61222204, 61432016)和863 计划(2013AA014301)资助项目. （2009ZX01028-002-003, 2009ZX01029-001-003, 2010ZX01036-001-002, 2012ZX01029-001-002-002, 2014ZX01020201, 2014ZX01030101）
