一种自适应低相位噪声相参时钟源的设计OACSTPCD
Design of an adaptive coherent clock source with low phase noise
通过锁相环电路(PLL)，不仅将外部系统提供的具有高频率准确度但相位噪声较差的主时钟信号转化为高频率准确度、低相位噪声的内部时钟信号，同时也满足了内外部系统的相参要求。通过仿真和测试，重点分析了锁相环电路中环路滤波器的环路带宽对输出信号相位噪声的影响。测试结果显示，当环路带宽为100 Hz时，锁相环的输出信号在偏离载波1 kHz处的相位噪声与其内部振荡器在此处的相位噪声基本一致；而当环路带宽为500 Hz时，输出信号在偏离载波1 kHz处的相位噪…查看全部>>
By the circuit of Phase-Locked Loop(PLL), the external system clock with high frequency accuracy but poor phase noise is converted into an internal clock signal with high frequency accuracy and low phase noise simultaneously. The internal clock source is coherent with the external source by the PLL as well. The effect of the PLL loop bandwidth on the phase noise of the output signal is analyzed emphatically through both simulations and measurements. Te…查看全部>>
周晓鹏;宋烨曦
中国人民解放军军事代表室，四川绵阳 621000四川九洲电器集团有限责任公司共性技术研究部，四川绵阳 621000
信息技术与安全科学
锁相环环路滤波器低相位噪声
Phase-Locked Looploop filterlow phase noise
《太赫兹科学与电子信息学报》 2016 (5)
753-757,5
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