电子器件2016，Vol.39Issue(6)：1527-1530,4.DOI:10.3969/j.issn.1005-9490.2016.06.047
一种带有亚稳态消除电路的TDC设计方案
A Design Scheme of TDC with Metastability-Elimination Circuits
摘要
Abstract
The technology of time interval measurement is of a great importance role in the atomicphysics,laserrang?ing,positioning and timing,and so on. As a result,the high precision Time-to-Digital Converter plays an important role in the scientific research and engineering practice. The power of TDC is 400μW,it works on 512 MHz,and it's measurement resolution is 250 ps,accuracy of measurement is 1μs;However,time interval measurement of TDC is often subject to metastability. Integral nonlinearity of TDC reduce to 0.25 LSB,and Differential nonlinearity reduce to 0.5 LSB by adding a phase judgment logic circuit. We can completely eliminate the metastability when TDC time in?terval.关键词
科学研究和工程实践/亚稳态消除/相位判断逻辑/时间间隔测量/时间数字转换电路Key words
scientific research and engineering practice/metastability elimination/phase judgment logic circuit/time interval measurement/Time-to-Digital Converter[TDC]分类
信息技术与安全科学引用本文复制引用
尤帅,艾国润,刘俐宏,杨赟秀,袁菲,甄少伟,贺雅娟,罗萍..一种带有亚稳态消除电路的TDC设计方案[J].电子器件,2016,39(6):1527-1530,4.基金项目
中央高校基本科研业务费项目(ZYGX2014J024) （ZYGX2014J024）
国家自然科学基金项目(61404025) （61404025）
