高技术通讯2016，Vol.26Issue(7)：625-630,6.DOI:10.3772/j.issn.1002-0470.2016.07.002
基于动态电路的高速发送端设计
Design of a high-speed transmitter based on dynamic circuits
摘要
Abstract
To lower the transmitter’ s delay of a high-speed serial interface, a new data transmission method under clock domain crossing was presented and realized in practical circuit design based on investigating and analyzing existing transmitter structures. This method can greatly reduce the delay for asynchronous FIFO during the data transmission under clock domain crossing. Moreover, the high-speed transmitter’ s serializing circuits were improved at transistor level by using dynamic circuits to relax critical paths’ timing requirement, so the transmitter’ s whole circuit can work under the higher frequency. The proposed transmitter’s circuit was manufactured with the 40nm CMOS technol-ogy, and the testing results demonstrate that the transmitter using the circuit can stably work at the rate of 13Gb/s.关键词
高速发送端/异步FIFO/并串转换/动态电路/跨时钟域Key words
high speed transmitter/asynchronous FIFO/serializer/dynamic circuits/clock domain crossing引用本文复制引用
孟时光..基于动态电路的高速发送端设计[J].高技术通讯,2016,26(7):625-630,6.基金项目
国家“核高基”科技重大专项课题(2014ZX01020201,2014ZX01030101),国家自然科学基金(61521092,61432016)资助项目。 （2014ZX01020201,2014ZX01030101）
