西安电子科技大学学报（自然科学版）2017，Vol.44Issue(1)：12-17,105,7.DOI:10.3969/j.issn.1001-2400.2017.01.003
一种采用双层仲裁机制的新型总线仲裁器
Novel bus arbiter with the two-level arbitration mechanism
摘要
Abstract
With the continuous increase in the complexity of the System‐on‐Chip ( SoC ) , the growing demand for bandwidth and the unpredictable wire delay have made buses the bottleneck of SoC properties;researches on efficient bus arbiters , which play a decisive role in the properties of SoC , are of great significance . In view of the decisions made by arbiters are determined by arbitration algorithms which have little reliance on hardware structures , a software simulation platform is provided in this paper to verify the properties of arbiters , on which a novel arbiter based on the structure and trans‐level judgment of the two‐level arbiter is proposed . Simulation results show that the novel arbiter would reduce the standard deviation between the actual granted ratio and the required bandwidth ratio by 54.4% and 50.8% respectively in comparison with two traditional arbiters , indicating the approximation between granted ratio and the required bandw idth ratio .关键词
系统芯片/总线/仲裁器/双层仲裁/带宽比Key words
system-on-chip ( SoC)/bus/arbiter/two-level arbitration/bandwidth ratio分类
信息技术与安全科学引用本文复制引用
刘露,周小锋,朱樟明,周端,杨银堂..一种采用双层仲裁机制的新型总线仲裁器[J].西安电子科技大学学报（自然科学版）,2017,44(1):12-17,105,7.基金项目
国家自然科学基金资助项目 （）
