现代电子技术2017，Vol.40Issue(4)：159-162,4.DOI:10.16652/j.issn.1004-373x.2017.04.040
基于USB 3.0接口的高速数据传输系统设计
Design of high-speed data transmission system based on USB 3.0 interface
宋中喆 1裴东兴 2杨少博1
作者信息
- 1. 中北大学 电子测试技术国家重点实验室，山西 太原 030051
- 2. 中北大学 仪器科学与动态测试教育部重点实验室，山西 太原 030051
- 折叠
摘要
Abstract
Since the current memory test system has the prominent problems of low data transmission speed and frequent fault occurrence,a high⁃speed data transmission system based on USB 3.0 interface was designed. The FPGA is taken as the main control chip of the design. The modes of negative delay and Ping⁃Pong cache are adopted to cache the data transformed through A/D into the DDR2 SDRAM with high speed. The general programming interface GPIF II and manual DMA channel were designed to realize the high⁃speed data transmission based on USB 3.0 synchronous slave FIFO mode. The system analysis, test and experimental results show that the system has realized the high⁃speed and reliable data transmission,and can effectively solve the high⁃speed data transmission problem occurring after large⁃capacity data acquisition.关键词
存储测试/USB 3.0接口/高速数据传输/负延迟/乒乓缓存Key words
memory testing/USB 3.0 interface/high-speed data transmission/negative delay/Ping-Pong cache分类
信息技术与安全科学引用本文复制引用
宋中喆,裴东兴,杨少博..基于USB 3.0接口的高速数据传输系统设计[J].现代电子技术,2017,40(4):159-162,4.
