国防科技大学学报2017，Vol.39Issue(1)：67-73,7.DOI:10.11887/j.cn.201701011
片上多核处理器的非阻塞环设计与物理实现
Design and physical implementation of non-blocking ring on a multicore processor
摘要
Abstract
A bi-directional non-blocking ring architecture was proposed for the multicore processor with relative less amount of high-performance cores.The architecture consists of five ring layers of three different types for commands, huge data and small data transportation, respectively.The source routing strategy was employed and an equipment state control interconnection was designed for congestion management.The router has a bufferless and contention-free structure and each hop only takes one clock cycle, thus minimizing the transmission delay and realizing deterministic routing.Considering the long links and high bandwidth of the ring, experiments were carried out to find a proper repeater insertion method, and the crosstalk optimizing methods, such as inverter insertion crosswise between two neighborhood lines and arranging neighborhood lines in signal transport direction, were studied to conduct physical design for the ring and delay optimization for the long links.Implementation results show that the designed ring′s bandwidth is 256 GByte/s@1 GHz, which can fulfill the data communication demands of the digital signal processing applications.关键词
非阻塞环/片上网络/延时优化/串扰优化Key words
non-blocking ring/networks-on-chip/delay optimization/crosstalk optimization分类
信息技术与安全科学引用本文复制引用
陈胜刚,刘必慰,齐娟,华迎召,刑素芳,丁艳平..片上多核处理器的非阻塞环设计与物理实现[J].国防科技大学学报,2017,39(1):67-73,7.基金项目
国家自然科学基金资助项目(61133007,61402499) （61133007,61402499）
