桂林电子科技大学学报2017，Vol.37Issue(1)：36-39,4.
容错处理器阵列的重构抽象模型
Abstraction model for reconfiguration VLSI array
摘要
Abstract
A novel abstraction model is proposed to accelerate the reconfiguration algorithms of VLSI.To construct the abstraction model, several physical rows of the array are extracted by the abstraction method, and the edge that represents the relation of communication is added between the extracted rows.Experimental results show that the abstraction model decreases the size by 90 percent compared to the original array and the complexity of reconfiguration is reduced.关键词
超大规模集成处理器阵列/降阶重构/容错/抽象技术Key words
VLSI processor array/degradation reconfiguration/fault tolerant/abstraction technique分类
信息技术与安全科学引用本文复制引用
白章顺,钱俊彦..容错处理器阵列的重构抽象模型[J].桂林电子科技大学学报,2017,37(1):36-39,4.基金项目
国家自然科学基金(61562015) （61562015）
广西自然科学基金(2015GXNSFDA139038) （2015GXNSFDA139038）
桂林电子科技大学研究生教育创新计划(YJCXS201537) （YJCXS201537）
