桂林电子科技大学学报2017，Vol.37Issue(1)：40-43,4.
高性能阵列重构的SAT描述模型
Satisfiability-based description model for reconfiguring power efficient VLSI array
摘要
Abstract
In order to reduce the energy consumption of reconstruction of the fault tolerant processor array, the SAT model of the power efficient VLSI array based on the thought of satisfiability is proposed.And the reconfiguration problem of array contained the faulty processor element is transformed into a combination and optimization problem of logic columns by combining the idea of satisfiability, which is further converted into the SAT model of the power efficient target array by using Boolean expressions.The analysis shows that the power efficient target array can be constructed by high-performance and efficient satisfiability solver with the SAT model of the power efficient target array.关键词
重构/可满足性/超大规模集成处理器阵列/容错Key words
reconfiguration/satisfiability/VLSI processor array/fault tolerance分类
信息技术与安全科学引用本文复制引用
胡佳,钱俊彦,周志德..高性能阵列重构的SAT描述模型[J].桂林电子科技大学学报,2017,37(1):40-43,4.基金项目
国家自然科学基金(61562015) （61562015）
广西自然科学基金(2015GXNSFDA139038) （2015GXNSFDA139038）
桂林电子科技大学研究生教育创新计划(YJCXS201537) （YJCXS201537）
