计算机工程2017，Vol.43Issue(2)：105-110,119,7.DOI:10.3969/j.issn.1000-3428.2017.02.018
基于2.5D封装系统的存储型计算研究
Research on In-memory Computing Based on 2.5D Integrated System
摘要
Abstract
For data-intensive applications,the large amounts of energy and latency spent in transporting data between off-chip memory and on-chip computing elements cause a limitation referred to as the yon Neumann bottleneck.Even in the 2.5D integrated system,the bottleneck also exists.Aiming at this problem,this paper proposes a novel hardware acceleration framework that enables computing in off-chip memory array for 2.5D system.It divides the memory into multiple banks and puts an accelerator designed for H.264 decoder in the memory to utilize the high bandwidth provided by the memory array.Simluation result shows that,compared with traditional software implementation method,this framework achieves 7.1X improvement in performance and 80.5％ reduction in energy consumption,and it only increases 2％ accelerator area.关键词
存储型计算/冯·诺依曼瓶颈/2.5D封装系统/H.264解码/数据密集型应用Key words
in-memory computing/von Neumann bottleneck/2.5D integrated system/H.264 decoding/data-intensive application分类
信息技术与安全科学引用本文复制引用
尹颖颖,虞志益..基于2.5D封装系统的存储型计算研究[J].计算机工程,2017,43(2):105-110,119,7.基金项目
广东顺德中山大学-卡内基梅隆大学国际联合研究院项目(20150303) （20150303）
三星电子横向课题(SLSI-201403DD013). （SLSI-201403DD013）
