计算机与数字工程2017，Vol.45Issue(3)：502-505,511,5.DOI:10.3969/j.issn.1672-9722.2017.03.020
一种优化的AES算法及其FPGA实现
An Optimized AES Algorithm and Its FPGA Implementation
张伟 1高俊雄 1王耘波 1武文斌1
作者信息
- 1. 华中科技大学光学与电子信息学院 武汉 430074
- 折叠
摘要
Abstract
For the encryption and decryption structure of AES is not consistent,an optimized AES algorithm with a unified encryption and decryption process is proposed in this paper.Using the fully pipelined architecture, the proposed circuit achieves an effective tradeoff between speed and resources, among which the S-box and inverse S-box are implemented applying the finite field algorithm based on regular basis.With the analysis of the path delay of each module, the AES round transformation is divided into 6 stages.Results implemented in the Xilinx`s XC7VX485T FPGA show that the hardware resource consumption is 19006LUTs,the maximum frequency is 724.323MHz and the throughput can get to 92.713Gbps, thus obtaining a very good acceleration effect.关键词
AES算法/全流水线/FPGAKey words
AES/full pipelining/FPGA分类
信息技术与安全科学引用本文复制引用
张伟,高俊雄,王耘波,武文斌..一种优化的AES算法及其FPGA实现[J].计算机与数字工程,2017,45(3):502-505,511,5.
