微型机与应用Issue(5)：60-64,5.DOI:10.19358/j.issn.1674-7720.2017.05.019
结构优化的维特比译码器的实现方案
Implementation method of structure optimization of Viterbi decoder
黄增先 1王进华1
作者信息
- 1. 福州大学 电气工程与自动化学院,福建 福州 350108
- 折叠
摘要
Abstract
In order to solve the problem of speed control in the decoding process of Viterbi decoder,a structure optimized Viterbi decoder is designed.Through the direct interconnection of the butterfly units,it is not necessary to store the path metric value during the state transition process,and the storage and reading logic of the path metric value is simplified.And the reuse times of butterfly processing units can be configured flexibly,according to different application requirements.Finally,combined with the FPGA platform,using Verilog hardware description language and Vivado software to design and implement the decoder.Implementation results show that the decoder occupies 1 564 LUTs of the FPGA,and can decode effectively under 100 MHz system clock.关键词
维特比/回溯/蝶形单元/加比选/状态转移因子/FPGAKey words
Viterbi/trace-back/butterfly unit/Add-Compare-Select(ACS)/state transfer factor/FPGA分类
信息技术与安全科学引用本文复制引用
黄增先,王进华..结构优化的维特比译码器的实现方案[J].微型机与应用,2017,(5):60-64,5.
