计算技术与自动化2017，Vol.36Issue(1)：113-117,5.DOI:10.3969/j.issn.1003-6199.2017.01.023
基于双线性插值算法的缩放IP核设计
Scaler IP Core Design Based on Bilinear Interpolation Algorithm
摘要
Abstract
This thesis designed an IP core based on bilinear interpolation algorithm.By decreasing the number of multiplers,this design optimized the implementation of the algorithm.The general two line buffer has the following drawbacks: not satisfying the quest of high real-time quality,high cost of frame memory and need of logic control for frame memory.So,this thesis designed a data buffer array called RAM FIFO.This thesis used multiple RAM to ensure the control of time-ordered and to save correctly the data of picture,which can make the data buffer more effective.At last,the time-ordered simulation of the design and the test result were introduced.The quality of resizing pictures is good.Comparing this IP core with the existed one,the Mean Absolute Error is very small.关键词
图像缩放/ScalerIP核/双线性插值算法/RAMFIFOKey words
picture resizing/scaler IP core/bilinear interpolation algorithm/RAM FIFO分类
信息技术与安全科学引用本文复制引用
邹学瑜,刘昌禄,胡敬营..基于双线性插值算法的缩放IP核设计[J].计算技术与自动化,2017,36(1):113-117,5.
