电子学报2017，Vol.45Issue(2)：452-458,7.DOI:10.3969/j.issn.0372-2112.2017.02.026
一种应用于TDC的低抖动延迟锁相环电路设计
Design of a Low Jitter Delay Locked Loop for TDC
摘要
Abstract
A delay-locked loop circuit of wide dynamic locking range and low static phase error is designed for Time to Digital Converter (TDC) application adopting dual delay lines,anti-lock control circuit structure and applying symmetrical matching techniques to key modules such as Charge Pump (CP),simultaneously.Simulation and Multi Project Wafer (MPW) tapeout are completed based on TSMC 0.35μm CMOS process.The test results show that DLL's frequency locking range is 40MHz-200MHz with its static phase error 161ps@125MHz.Driven by noise-free input clock,and operating on 200MHz,DLL's maximum peak-to-peak and root-mean-square jitters are 85.3ps and 9.44ps,respectively adapting the subnanosecond time-resolved TDC's application requirement.关键词
延迟锁相环/时间数字转换器/静态相位误差/宽动态范围/时钟抖动Key words
delay-locked loop (DLL)/time-to-digital converter (TDC)/static phase error/wide dynamic range/clock jitter分类
信息技术与安全科学引用本文复制引用
吴金,张有志,赵荣琦,李超,郑丽霞..一种应用于TDC的低抖动延迟锁相环电路设计[J].电子学报,2017,45(2):452-458,7.基金项目
江苏省自然科学基金(No.BK2012559) （No.BK2012559）
中央高校基本科研业务费专项资金资助,江苏省普通高校研究生科研创新计划资助项目(No.SJLX15_0098) （No.SJLX15_0098）
