计算机应用与软件2017，Vol.34Issue(2)：147-151,5.DOI:10.3969/j.issn.1000-386x.2017.02.025
基于DDR3高速电路拓扑结构的优化与仿真
OPTIMIZATION AND SIMULATION OF HIGH-SPEED CIRCUIT TOPOLOGY BASED ON DDR3
孙静 1黄文清1
作者信息
- 1. 湖南大学电气与信息工程学院 湖南长沙410006
- 折叠
摘要
Abstract
By studying the public version of DDR3 PCB which is designed by JEDEC company with register memory (RDIMM) B0,the corresponding Fly-By Topology of clock signal line is extracted according to the IBIS simulation model of RDIMM.Using SigXplorer software to simulate and analyze the original Fly-By Topology.Then,according to the existing topology features,a new topology called Fly-Shu is designed.In the end,comparing the rectangular waveform come from the reflected simulation and Eye waveform come from the crosstalk simulation with the simulation result of the original Fly-By Topology,it is found that the new designed Fly-Shu Topology is better at restraining the influence of reflection and crosstalk,so that the higher integrity of high speed signal integrity in transmission is ensured.At the mean time,the new design of the Fly-Shu Topology can offer a good reference in designing and simulating the PCB of high speed signal.关键词
高速电路/差分对信号/信号完整性/眼图/Cadence软件Key words
High-speed circuit/Differential pair signals/Signal integrity/Eye pattern/Cadence software分类
信息技术与安全科学引用本文复制引用
孙静,黄文清..基于DDR3高速电路拓扑结构的优化与仿真[J].计算机应用与软件,2017,34(2):147-151,5.
