太赫兹科学与电子信息学报2017，Vol.15Issue(1)：120-124,5.DOI:10.11805/TKYDA201701.0120
一种流水线ADC后台数字校准算法的实现
Implementation of digital backstage calibration algorithm for pipeline ADC
摘要
Abstract
An improved digital backstage calibration algorithm to calibrate high-speed pipeline Analog to Digital Converter(ADC) is introduced.This algorithm combines the slow but accurate ADC as a reference with an adaptive filter based on Least Mean Square(LMS) algorithm to rectify errors of the pipeline ADC,thereby improving the speed and accuracy of the calibration.The Verilog HDL is used to design the Register Transfer Level(RTL) circuit.At the same time,the co-simulation method of Simulink and Modelsim is adopted to verify the circuit.The verification result shows that the improved calibration algorithm has better convergence speed and accuracy compared with that of fixed-step calibration algorithm.关键词
流水线ADC/数字校准/LMS算法Key words
pipelined Analog to Digital Converter/digital calibration/Least Mean Square algorithm分类
信息技术与安全科学引用本文复制引用
张文杰,邓准,谢亮,金湘亮..一种流水线ADC后台数字校准算法的实现[J].太赫兹科学与电子信息学报,2017,15(1):120-124,5.基金项目
国家自然科学基金资助项目(61274043 （）
61233010) （）
湖南省自然科学杰出青年基金资助项目(2015JJ1014) （2015JJ1014）
