电子学报2017，Vol.45Issue(3)：540-545,6.DOI:10.3969/j.issn.0372-2112.2017.03.005
Gzip压缩的硬件加速电路设计
Hardware-Accelerated Circuit Design for Gzip Compression
摘要
Abstract
The hardware implementation of lossless data compression is wildly used in big data computing and communication,since it combines the speed and power advantage of the dedicated circuit.This paper proposed a hardware compression circuit based on GNUzip(Gzip) lossless data compression algorithm.The dual Hash functions,parallel match processing,hardware storage oriented LZ77 compression data format and high-performance data adaptor were involved to accelerate the compression speed with the advantages of parallel calculation and pipeline structure.The hardware compression circuit,based on Verilog HDL,was tested and verified by field programmable gate array (FPGA).The test data shows that,compared with software implementation,the compression speed of hardware circuit is improved significantly while the compression rate is 65.9％.The average speed is up to 171Mb/s that can satisfy the real-time compression requests of network communication and data storage.关键词
无损压缩/Gzip/硬件/LZ77/FPGAKey words
lossless compression/Gzip/hardware/LZ77/FPGA分类
信息技术与安全科学引用本文复制引用
李冰,王超凡,顾巍,董乾..Gzip压缩的硬件加速电路设计[J].电子学报,2017,45(3):540-545,6.基金项目
国家自然科学基金(No.61571116) （No.61571116）
