电子学报2017，Vol.45Issue(6)：1311-1320,10.DOI:10.3969/j.issn.0372-2112.2017.06.005
面向分组密码的可重构异构多核并行处理架构
Reconfigurable Asymmetrical Multi-core Architecture for Block Cipher
摘要
Abstract
Among the existing reconfigurable block cipher hardware structures,the special instruction processor does not achieve high throughput rate,while resource utilization of the reconfigurable block cipher processing array is low and mapping process is very complicated.Therefore,the reconfigurable asymmetrical multi-core architecture (RAMCA) for block cipher was designed.Mapping processes of typical structures,which were SP (AES-128),Feistel (SMS4),L-M (IDEA) and MISTY (KASUMI),was analyzed.Hardware implementation was designed and synthesized in a 65nm CMOS process.The experimental area is about 1.13sq mm while frequency reaches 1GHz.After the influence of the process is eliminated,the performance of RAMCA is higher than that of other special instruction processors and most of the reconfigurable block cipher processing arrays,such as Celator,RCPA,BCORE,etc.关键词
分组密码/异构多核/可重构/并行处理/密码处理器Key words
block cipher/heterogeneous multi-core/reconfigurable/parallel processing/cipher processor分类
信息技术与安全科学引用本文复制引用
冯晓,李伟,戴紫彬,马超,李功丽..面向分组密码的可重构异构多核并行处理架构[J].电子学报,2017,45(6):1311-1320,10.基金项目
国家自然科学基金(No.61404175) （No.61404175）
