无线电通信技术2017，Vol.43Issue(4)：86-90,5.DOI:10.3969/j.issn.1003-3114.2017.04.21
多相并行FIR滤波器的FPGA高速实现方法
FPGA Implementation of Polyphase Parallel FIR Filter
摘要
Abstract
Compared with the serial FIR filter,the sample frequency of L-channel polyphase parallel FIR filter is increased by a factor of L.The implementation structure of polyphase parallel filter based on polynomial decomposition is simple,with low computation complexity and short delay.The paper summarizes and deduces the optimal structure of polyphase parallel filter from 2 channels to 8 channels.Further,the paper proposes the implementation method of the optimal structure of polyphase parallel filter fit for processing in FPGA.The computer simulation shows the proposed implementation method of polyphase parallel filter is fit for processing in FPGA with high-speed.关键词
FIR滤波器/多相分解/FPGA/高速Key words
FIR filter/polyphase decomposition/FPGA/high-speed分类
信息技术与安全科学引用本文复制引用
张娜,李春祎..多相并行FIR滤波器的FPGA高速实现方法[J].无线电通信技术,2017,43(4):86-90,5.基金项目
中国电子科技集团公司航天信息应用技术重点实验室开放基金(EX166290012) （EX166290012）
