电讯技术2017，Vol.57Issue(7)：830-833,4.DOI:10.3969/j.issn.1001-893x.2017.07.017
一种交错并行高速TPC译码器的设计
Design of a High-speed Interleaved Parallel TPC Decoder
熊玉平1
作者信息
- 1. 中国船舶工业系统工程研究院,北京 100036
- 折叠
摘要
Abstract
Turbo product code (TPC) is applied extensively in bandlimited communication systems as a high-rate code.But most TPC decoders have the problems of complex structure, high resource consumption and large processing latency.For these problems,this paper proposes an interleaved parallel decoder adopting pipelined architecture.By using the reordered test sequences and optimized algorithm such as replacement of the calculation of Euclidean distance by correlation operation, the complexity is reduced, processing latency is shortened and resource consumption is reduced by 35%.Based on the proposed structures, a hardware implementation of TPC decoder on Xilinx XC5VSX95T FPGA is presented.The results show that the proposed decoder architecture can achieve a decoding throughput of 80 Mbit/s, and the decoding throughput can be improved further by increasing the number of sub-decoders.关键词
Turbo乘积码(TPC)/交错并行结构/测试序列/相关运算Key words
Turbo product code(TPC)/interleaved parallel architecture/test sequence/correlation operation分类
信息技术与安全科学引用本文复制引用
熊玉平..一种交错并行高速TPC译码器的设计[J].电讯技术,2017,57(7):830-833,4.
