单片机与嵌入式系统应用2017，Vol.17Issue(7)：19-22,4.
FPGA的多路数据并行录取和时序资源优化
Parallel Data Transmission Timing and Resource Optimization Based on FPGA
苏阳 1赵英潇 1黄睿 1张月 1陈曾平1
作者信息
- 1. 国防科技大学 自动目标识别重点实验室,长沙 410073
- 折叠
摘要
Abstract
The PCIe bus is widely used in the radar system,but the internal integrated FPGA PCIe core is limited.So ti is difficult to meet the needs of a variety of data parallel transmission of radar.In this paper,an improved PCIe DMA data transmission method is proposed,which ensures the data can be achieved in the parallel high speed transmission using Xilinx FPGA integrated PCIe core.In order to solve the problem of timing in the process of implementation,a multi-level FIFO cascade method is proposed.Based on the characteristics of Xilinx FPGA clock network,the clock resource is optimized for the system expansion and upgrade.关键词
FPGA/PCIe/并行录取/时序优化Key words
FPGA/PCIe/parallel transmission/timing optimization分类
计算机与自动化引用本文复制引用
苏阳,赵英潇,黄睿,张月,陈曾平..FPGA的多路数据并行录取和时序资源优化[J].单片机与嵌入式系统应用,2017,17(7):19-22,4.
