太赫兹科学与电子信息学报2017，Vol.15Issue(3)：507-512,6.DOI:10.11805/TKYDA201703.0507
一种500 Mbps至4 Gbps连续速率的多模式CDR电路
A 500M to 4Gbps continuous-rate multimode PI-CDR implementation in 130nm CMOS
摘要
Abstract
A continuous-rate Clock Data Recovery(CDR) circuit is proposed, which covers a data rate of 500 Mbps to 4 Gbps. The proposed CDR,implemented in 130 nm Complementary Metal Oxide Semiconductor(CMOS),is based on phase interpolation and utilizes digital voter and phase control logic instead of charge pump and analog filter, which is meaningful to transplantation between different technologies. To reduce the frequency range of the clock of Phase Lock Loop(PLL) outputs and avoid the Phase Interpolator(PI) getting into the nonlinear region,multimode is designed to limit the frequency range of the sampling clock only from 500M to 1GHz. The PI realizes an accuracy of 7 bit and a good linearity, while the peak-to-peak jitter of the recovered clock of is about 25.6ps at 4Gbps. The CDR realizes a BER<10-10 and is able to track a maximum frequency offset of ±976.6ppm between the input data and the sampling clock. The power consumed by the proposed CDR is 13.28mW/Gbps. A 5mm2 test chip is also fabricated, where the CDR core occupies 0.359mm2 of area.关键词
时钟数据恢复/相位插值/连续速率/多模式/互补金属氧化物半导体Key words
Clock-Data-Recovery/Phase Interpolator/continuous-rate/multimode/Complementary Metal Oxide Semiconductor分类
信息技术与安全科学引用本文复制引用
李天一,许晓冬,尹韬,辛福彬,李威,杨海钢..一种500 Mbps至4 Gbps连续速率的多模式CDR电路[J].太赫兹科学与电子信息学报,2017,15(3):507-512,6.基金项目
自然科学基金资助项目(No.61271149.61474120) （No.61271149.61474120）
