东南大学学报（自然科学版）2017，Vol.47Issue(4)：649-654,6.DOI:10.3969/j.issn.1001-0505.2017.04.004
双通道可重构14 bit 125 MS/s流水线ADC
Dual-channel reconfigurable 14 bit 125 MS/s pipelined ADC
摘要
Abstract
A dual-channel reconfigurable 14 bit 125 MS/s pipelined ADC(analog to digital converter) is presented.The dual channel 14 bit ADC can work in parallel dual 14 bit 125 MS/s mode, time interleaved 14 bit 250 MS/s mode, and sum 15 bit 125 MS/s mode.To reject the influence of the channel mismatch error, a mix-signal for-ground calibration technique is proposed.To reduce the digital output pins, the high speed serial transmitter is introduced to drive the digital output code, which can work in 1.75, 2 and 3.5 Gbit/s modes.The ADC is fabricated with 0.18 μm 1.8 V 1P5M CMOS(complementary metal oxide semiconductor) technology.Test results show that the ADC achieves the signal to noise ratio (SNR) of 72.5 dBFS and spurious free dynamic range (SFDR) of 83.1 dB for parallel dual 14 bit 125 MS/s mode, the SNR of 71.3 dBFS and SFDR of 77.6 dB for time interleaved 14 bit 250 MS/s mode, the SNR of 75.3 dBFS and SFDR of 87.4 dB for sum 15 bit 125 MS/s mode, with 10.1 MHz input at full sampling speed.The ADC consumes the total power of 461 mW, while the single 14 bit ADC core consumes the power of 210 mW and occupies an area of 1.3×4 mm2.关键词
流水线模数转换器/可重构/时间交织/电流模发送器Key words
pipelined analog-to-digital converter/reconfigurable/time-interleaved/current mode transmitter分类
信息技术与安全科学引用本文复制引用
张惠国,陈珍海,孙伟锋,周德金,于宗光,魏敬和..双通道可重构14 bit 125 MS/s流水线ADC[J].东南大学学报（自然科学版）,2017,47(4):649-654,6.基金项目
国家自然科学基金资助项目(61474092)、安徽高校自然科学研究重点资助项目(KJ2017A396)、教育部留学回国人员科研启动基金资助项目. （61474092）
