计算机工程2017，Vol.43Issue(1)：109-114,119,7.DOI:10.3969/j.issn.1000-3428.2017.01.019
基于FPGA的卷积神经网络加速器
FPGA-based Accelerator for Convolutional Neural Network
摘要
Abstract
Aiming at the problem that existing software implementation schemes of Convolutional Neutral Network (CNN) cannot meet the requirements of computing performance and power consumption,this paper proposes a Field Programmable Gate Array (FPGA)-based accelerator for CNN.The convolution computation unit is paralled accelerated in the coarse-grained paralleled level and the whole process is fully pipelined.This optimization allows 20 multiplyaccumulations to finish in a single cycle,which greatly improves calculation efficiency.Experimental results for MNIST handwritten digits character recoghition show that the proposed FPGA-based accelerator can achieve peak performance of 0.676 GMAC/s under 75 MHz,and be 4 times faster than general CPU platform,while the power consumption is only 2.68percent of it.关键词
卷积神经网络/现场可编程门阵列/加速器/流水线/并行化Key words
Convolutional Neutral Network (CNN)/Field Programmable Gate Array (FPGA)/accelerator/pipeline/parallelization分类
信息技术与安全科学引用本文复制引用
余子健,马德,严晓浪,沈君成..基于FPGA的卷积神经网络加速器[J].计算机工程,2017,43(1):109-114,119,7.基金项目
国家“863”计划项目“CMC系列芯片的设计、开发与制造”(2012AA041701). （2012AA041701）
