计算机工程与应用2017，Vol.53Issue(16)：237-240,257,5.DOI:10.3778/j.issn.1002-8331.1612-0104
TP RAM的低功耗优化设计及应用
Low power optimization of TP RAM and application.
摘要
Abstract
As the area and power consumption of TP RAM in SoC are large, a new design method of optimization is pro-posed. In order to achieve the function of the original TP RAM and keep the external interface unchanged, TP RAM is re-placed with SP RAM, and read-write interface logics of conversion are added around SP RAM. For less power, adaptive clock-gating is used and address bus is encoded through Gray code. The method discussed in this paper is used in the multi core SoC chip which has been successfully taped out in TSMC 28 nm HPC process. The chip occupies 10.5 mm×11.3 mm of die area and consumes 17.07 W. The testing results indicate that the area of optimized RAMs is reduced by 25.2%, and the power saving is 43.07%.关键词
伪双口随机存储器(TPRAM)/单口随机存储器(SPRAM)/接口转换逻辑/自适应门控时钟/格雷码Key words
Two Ports Random Access Memory(TP RAM)/Single Port Random Access Memory(SP RAM)/interface logics of conversion/adaptive clock-gating/Gray code分类
信息技术与安全科学引用本文复制引用
周清军,刘红侠..TP RAM的低功耗优化设计及应用[J].计算机工程与应用,2017,53(16):237-240,257,5.基金项目
国家自然科学基金(No.61376099,No.6143000024) （No.61376099,No.6143000024）
陕西省教育厅专项基金项目(No.16JK2138). （No.16JK2138）
