高技术通讯2017，Vol.27Issue(1)：20-26,7.DOI:10.3772/j.issn.1002-0470.2017.01.003
硬件友好的3GPP-LTE Turbo交织器设计
Design of a hardware-friendly turbo interleaver for 3GPP-LTE
摘要
Abstract
The optimization of the hardware design of quadratic permutation polynomial (QPP) interleavers for 3GPP-LTE was studied, and a scheme for design of zero-delay, low-complexity QPP interleavers was presented.The design scheme can simplify the complex computations defined by OPP interleavers at the algorithm level, and it makes an optimized OPP interleaver be readily mapped onto its hardware circuit under a low cost because of the benefit from the optimization.The implementation result shows that the proposed scheme can greatly reduce the complexity of hardware implementation compared to traditional approaches, and the area of the designed interleaver is only 0.040mm2 under the technology of CMOS 40mm.Furthermore, the designed interleaver reveals its zero-delay property, and the ability to effectively improve the efficiency of Turbo decoding.Actually, after putting the whole Turbo decoder into practice, the decoder can work at 400 MHz, the area of which is only 0.82mm2 while the peak decoding throughput can reach 572.85Mbps with 10 half-iterations.关键词
长期演进(LTE)/Turbo/二次置换多项式(QPP)/交织器/ASIC设计/零延时/低复杂度Key words
long term evolution (LTE)/Turbo/quadratic permutation polynomial (QPP)/interleaver/ASIC design/zero delay/low complexity引用本文复制引用
姚彦斌,周一青,林江南,萧放..硬件友好的3GPP-LTE Turbo交织器设计[J].高技术通讯,2017,27(1):20-26,7.基金项目
国家自然科学基金(61431001)和北京市青年拔尖人才(2015000021223ZK31)资助项目. （61431001）
