测控技术2017，Vol.36Issue(8)：94-98,5.
多核片上系统时钟网络结构模型与仿真分析
Clock Network Structure and Simulation on MPSoC
摘要
Abstract
Flexibility is becoming more and more important to the overall performance of modern MPSoC clock networks.The flexibility of global and local networks based on structural modeling is studied.Through the establishment of multi-level structure,the structure is separated into three layers,i.e.trunk,branch and access.The performance of clock network is evaluated in terms of the number of logical blocks,the number of rows in a single row,the number of logic element input clocks in the logic block,and the number of clocks.Stratix V E FPGA is taken as an example of a comprehensive analysis of the clock network,and the analysis results show that the four quadrant symmetric structure is the optimal clock network structure by fully considering about the tradeoff of overall performance,and can be used as a general structure in the current mainstream MPSoC.关键词
多核片上系统/时钟网络/仿真分析Key words
MPSoC/clock network/simulation analysis分类
信息技术与安全科学引用本文复制引用
余乐,王瑶,陈岩,吴超,李洋洋,李阳光..多核片上系统时钟网络结构模型与仿真分析[J].测控技术,2017,36(8):94-98,5.基金项目
北京市自然科学基金资助项目(4174086) （4174086）
国家自然科学基金资助项目(61473009) （61473009）
